Capacitors, each of which generally comprises a dielectric layer sandwiched by a pair of conducting plates, are one of the most fundamental components in electronics. The same can also be said in microelectronics. As the trend in the fabrication of semiconductor devices is toward ever-increasing density of circuit components that can be tightly packed per unit area, there are great demands to develop technologies that can reduce the surface area to be taken by individual circuit components. As a result, deep trench technologies have been developed which result in structures, particularly large area capacitors, that are vertically oriented with respect to the plane of the substrate surface. Capacitors can also be formed in a crown-type stacked structure that are arranged in the direction generally parallel to the plane of the substrate surface.
The capacitance value provided by a given capacitor is determined by the following well known formula: EQU C=KA/t
where C is the capacitance, K is the relative dielectric constant of the insulator, A is the area of overlay of the conducting plates, and t is the thickness of the dielectric layer.
A deep trench capacitor typically comprises a dielectric layer formed on the sidewalls of a deep trench, which is formed into and surrounded by a highly doped buried plate (which constitutes the first conducting plate), and a highly doped poly fill (which constitutes the second conducting plate), which fills the deep trench. As indicated by the above equation, the capacitance of the deep trench capacitor is determined by the total sidewall surface of the trench, which, in turn, is determined by the diameter, or more specifically the circumference, of the deep trench.
As the semiconductor fabricating technology moves into deep sub-micron, it is increasingly recognized that the present technology for making deep trench capacitors may be inadequate. For deep sub-micron semiconductor devices, a deep trench can have a length-to-diameter aspect ratio of 35:1 or even greater. With current technology, the diameter (or width or circumference) of the trench generally decreases with depth, as shown in FIG. 1. Such a tapered cross-sectional area causes a significant decrease in the overall sidewall surface of the trench, and, consequently, the capacitance provided by the deep trench capacitor. This problem is expected to become even more profound as we move into the next generation ULSI fabrication technology with a critical dimension of 0.15-micron or even finer.
In an article entitled "0.228 .mu.m Trench Cell Technologies with Bottle-Shaped Capacitor for 1 Gbit DRAMs", by T. Ozaki, et al, IEDM, 95, PP661-664 (1995), the content thereof in incorporated herein by reference, the authors disclosed a method to increase the diameter of a deep trench. The method disclosed therein includes the steps of: (1) forming an 80 nm collar oxide at the upper portion of the trench by the selective oxidation; (2) performing a capacitor process which includes oxidation mask removal, native oxide removal, etc., during which process the collar oxide thickness reduces to 50 nm; and (3) in-situ phosphorous doped polysilicon is deposited and phosphorous doping into the trench side wall at the capacitor portion (plate electrode) is performed by the furnace annealing technology. The collar oxide prevents phosphorous doping at the upper portion of the trench; it also makes the electrical isolation between the plate electrode and the transfer transistor. The poly-silicon is removed by chemical dry etching and the diameter of the trench under the collar oxide is enlarged at the same time. The authors reported that the trench diameter is enlarged by 30%, thus forming a "bottled-shaped" deep trench.
One of the drawbacks of this technology and all the technologies derived therefrom is that the diameter enlargement is dictated by the differential etch rates between phosphorous-doped polysilicon and silicon. Typically, the phosphorous-doped polysilicon only improves the etch rate by a factor of two relatively to undoped silicon. This is further complicated by the fact that, during the annealing process, the phosphorous ions will laterally to the silicon portion, thus further reducing the etching selectivity causing it difficult to have a sharp boundary. As a result, the Ozaki et al process does not provide enough precision for application in small geometry technologies.
Another main drawback of the Ozaki et al process is that it requires a relatively thick (initially 800 .ANG.) oxide collar to protect the neck portion of the deep trench during the phosphorous-doping and the subsequent etching process. After the etching process to enlarge the bottom portion of the deep trench, the oxide collar remains. Because the relatively thick oxide collar in the Ozaki et al process grows into the sidewall of the deep trench, it further limits the dimension to which the deep trench can be downsized.
The technique invented by Ozaki et al as described in the article mentioned above was incorporated in U. S. Pat. No. 5,849,638, which discloses a method to further enhance the sidewall surface area of a deep trench. The method disclosed in the '638 patent, the content thereof in incorporated herein by reference, includes the steps of: (1) opening a deep trench mask at an angle for the first trench; (2) etching a trench using RIBE (reactive ion beam etching) with the wafer oriented 1 to 16 degrees off axis with respect to the ion source; (3) opening the deep trench mask at an angle for the second trench; (4) etching the trench using RIBE with the wafer oriented 1 to 15 degrees in the opposite direction; (5) oxide collar formation; and (6) chemical down-stream etching (CDE) to isotropically increase the size of the trench. Steps (5) to (6) were taken from and are identical to the procedure disclosed by Ozaki et al, which included the steps of forming an oxide collar and etching the entire trench sidewall not covered by the oxide collar. Again, as discussed above, as with the Ozaki et al technique, the method taught in the '638 patent may not provide enough precision in deep sub-micron applications.
Other prior art references also discuss the methods for fabricating deep trench capacitors for semiconductor applications. These include U. S. Pat. Nos. 5,064,777, 5,168,336, 5,310,289, 5,348,758, 5,525,531, 5,536,675, 5,614,431, 5,627,092, 5,646,063, 5,656,535, 5,674,769, 5,807,761, 5,828,094, 5,831,301, 5,837,575, etc. None of these patents taught or suggested any method that may be utilized to selectively enlarge the sidewall surface of a deep trench with the kind of precision required for deep sub-micron applications.